THE NOETON STACK · L1 / L5
L1 Memory-Centric Substrate
MEMORY-CENTRIC SUBSTRATE
Weights are no longer moved — they live inside compute.
The von Neumann machine treats memory as a passive warehouse: every computation hauls data to the CPU. For large models this is a disaster — weight tensors are huge and nearly static, the KV cache keeps growing, and moving them costs far more energy than computing on them. L1 inverts the hierarchy: weights and the KV cache become the resident center of the machine, with compute units embedded in the memory arrays, working in place.
Three proven technologies form this substrate: processing-in-memory (HBM-PIM, UPMEM) builds arithmetic into the memory banks; CXL pooling decouples capacity from a single chassis so the KV cache can stretch across boxes; wafer-scale integration (Cerebras WSE) shows an entire model can live on one piece of silicon. The Noeton synthesizes them into one unified weight-resident substrate.
POSITION IN STACK
L5 Intent Interface L4 Network Fabric · Tiered Cognition L3 Model-OS Runtime L2 Tensor Dataflow Fabric L1 Memory-Centric Substrate ◀ you are hereHBM-PIM arrays
Arithmetic inside the memory banks; attention runs at zero distance
CXL pooled memory
Capacity decoupled from the box; KV cache stretches elastically
Wafer-scale residence
The whole model on one piece of silicon — no off-chip hauling
Near-memory scheduler
Migrates KV blocks across tiers by access temperature
INTERACTIVE · LIVE
Why must weights live inside memory? Watch the energy race: the left hauls data across a bus for every op; the right computes in place.
Weights stay resident
Load once, reside indefinitely — "boot" becomes a session-level concept.
Bandwidth is performance
Decode throughput scales directly with substrate bandwidth — verify it in the roofline lab.
Capacity decoupled
The context-length ceiling moves from "one card's VRAM" to "pool capacity".