Twenty-eight words to read this machine.

Noeton

From Greek noesis, "the act of understanding". A machine redesigned from the hardware up around the LLM, proposed as the successor abstraction to the von Neumann machine.

In the Noeton — Everything on this site answers one question: what this machine should look like.

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模型原生架构（MNA）

The Noeton's organizing principle: memory-centric, model-native compute, model-as-OS, tiered cognition, intent interaction — five principles forming one coherent reference design.

In the Noeton — The line between accelerating parts and reorganizing the machine is drawn here.

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五层栈

The Noeton's vertical structure: L1 memory substrate → L2 dataflow fabric → L3 Model-OS → L4 network fabric → L5 intent interface.

In the Noeton — Each layer overturns one default assumption of the von Neumann era.

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内存墙

The systemic bottleneck formed as processor compute outgrows memory bandwidth (~52%/yr vs ~25%/yr), the gap compounding exponentially.

In the Noeton — The Noeton's first-principles starting point: LLM inference hits this wall head-on.

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Roofline 模型

Attainable performance = min(bandwidth × arithmetic intensity, peak compute). Slope = bandwidth-bound; flat roof = compute-bound; they meet at the ridge point.

In the Noeton — The courtroom of every architecture argument here — decode is pinned to the far left of the slope.

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算术强度

Operations per byte of memory traffic (FLOP/byte). Decides where a workload stands on the roofline.

In the Noeton — Hundreds for prefill, near-constant for decode — one metric, two physics.

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存内计算（PIM）

Arithmetic built into the memory arrays (bank level): data computes in place, no bus hauling. See Samsung HBM-PIM, SK hynix AiM, UPMEM.

In the Noeton — The endgame device of the L1 substrate — decode's GEMV is its killer workload.

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近存计算

Compute placed beside rather than inside memory: custom HBM base dies, processing in CXL controllers.

In the Noeton — A v2 refinement: near-memory arrives before in-memory; L1 is a progression.

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HBM

3D-stacked memory co-packaged via silicon interposer. From HBM4, custom base dies become standard — logic is entering the memory stack.

In the Noeton — Where the bandwidth premium lives, and PIM's natural host.

CXL

A cache-coherent interconnect on PCIe PHY supporting memory expansion, pooling, and sharing (Type 3 devices).

In the Noeton — The standard channel for L1 capacity decoupling; controllers (e.g., Montage MXC) are sampling.

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内存池化

Memory decoupled from the box into a cluster-level shared resource, allocated on demand. Azure's Pond proved the cloud economics.

In the Noeton — Moves the KV-cache ceiling from "one card's VRAM" to "pool capacity".

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晶圆级集成

The whole wafer as one chip (Cerebras WSE): massive on-die SRAM lets much of a model reside on silicon.

In the Noeton — The limiting case of L1's weight residence.

数据流架构

Hardware organized by the computation graph: data flows along compile-time-scheduled paths between units, not driven by an instruction stream. See Groq TSP, SambaNova RDU.

In the Noeton — The hardware form of the L2 fabric — compile-time planning traded for runtime determinism.

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确定性执行

Execution predictable cycle-by-cycle at compile time: no cache misses, no arbitration, no speculation.

In the Noeton — Turns latency from a statistic into a design value — contract, not best effort.

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管家核

The demoted general-purpose core in the Noeton: boot, monitoring, exceptions, and the legacy stack — no longer central to the datapath.

In the Noeton — The CPU's new job description.

KV 缓存

The session memory of autoregressive inference: each token's key-value pairs kept for future attention queries, growing linearly with context.

In the Noeton — A first-class citizen of L1 — tiered by temperature, stretched across machines.

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Prefill / Decode

Inference's two phases: prefill consumes the whole prompt in parallel (compute-bound); decode generates token-by-token (bandwidth-bound).

In the Noeton — "One request, two physics" — the basis of phase-split scheduling.

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Split Inference

Running prefill and decode in separate hardware domains/pools (Splitwise, DistServe, Mooncake; hardware-ized by NVIDIA Rubin CPX).

In the Noeton — P4's intra-tier form — now fully adopted by industry.

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Model-OS

A runtime with an LLM kernel: agents are processes, tools are syscalls, vector stores the filesystem, intent the executable format.

In the Noeton — L3 itself; its kernel triad (scheduling/privilege/memory) is the open battleground.

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上下文窗口

The token span a model can attend to in one pass — the "working memory / RAM" in the Model-OS view.

In the Noeton — The new scarce resource: context is the time slice.

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向量记忆

Storage indexed by embeddings: recalled by semantic similarity rather than addressed by path.

In the Noeton — The Model-OS "filesystem" — meaning-addressed, forgetting as GC.

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MCP

The open protocol unifying the model × tool surface with typed schemas; industry-adopted and moved to Linux Foundation governance within 13 months.

In the Noeton — The de-facto ABI of tool syscalls — adopted directly by the L3 tool gateway.

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智能体（Agent）

An execution entity spawned by intent, running with memory, suspendable and resumable — the process's counterpart in the Model-OS.

In the Noeton — "A process lives as a PID; an agent lives as a goal."

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记忆快照

A persistable copy of an agent's full state (context + episodic pointers), resumable elsewhere.

In the Noeton — The suspend/migrate/crash-recovery primitive of the agent world.

意图接口

A human interface whose unit of work is intent expressed against context: the machine compiles intent into visible, editable plans; irreversible acts return to the human.

In the Noeton — L5 — a paradigm change, not a better voice assistant.

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分层认知

Device (floor) → edge (regional pools) → cloud (full capability); requests land on the cheapest satisfying tier.

In the Noeton — P4 itself; the cross-tier cheapest-first scheduler is the open gap.

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降级模式

The declared offline floor on-device (dictation, local search, basic control) — deliberately limited, never zero.

In the Noeton — The other half of the network-mandatory contract: a transparent capability boundary.

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人在回路

Control handed over by side-effect grade: reversible acts run automatically; irreversible ones require human confirmation; authorization fully audited.

In the Noeton — L5's safety floor and the user-facing face of the Model-OS privilege model.

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