A Model-Native Architecture (MNA) for the AI era — a machine redesigned from the hardware up, around the large language model.
von Neumann machine → Noeton
For seventy years the computer has been a von Neumann machine. Foundation-model inference breaks the deal: the dominant cost is not arithmetic but moving vast, mostly static weight tensors and a growing KV cache. Autoregressive decode is bound by memory bandwidth, not FLOPs. The industry’s current answer — the “AI PC”, a von Neumann machine with an NPU bolted on — is a transitional form, not the final one.
Each principle is backed by existing systems research: HBM-PIM, UPMEM, CXL pooling, TPU/Groq/SambaNova dataflow, MemGPT/AIOS…
Weights and the KV cache are first-class citizens, served in place by processing-in-memory and disaggregated, pooled memory — not streamed through a core.
A tensor / attention dataflow fabric does the heavy lifting; the classical CPU is demoted to a housekeeping coordinator.
An LLM as the kernel: agents are processes, tools are syscalls, vector stores are the filesystem.
A small on-device model provides only a degraded-mode floor; full capability comes from networked weight pools across device, edge, and cloud.
The user’s unit of work is an intent expressed against context, not a command issued against data.
All diagrams are the paper’s original vector figures (TikZ → SVG).