Position / Vision Paper · v2 (June 2026 revision · new "Industry Trajectory" section)

Beyond the Computer:
The Noeton

A Model-Native Architecture (MNA) for the AI era — a machine redesigned from the hardware up, around the large language model.

von Neumann machine  →  Noeton

Why

A seventy-year contract, pushed to its breaking point

For seventy years the computer has been a von Neumann machine. Foundation-model inference breaks the deal: the dominant cost is not arithmetic but moving vast, mostly static weight tensors and a growing KV cache. Autoregressive decode is bound by memory bandwidth, not FLOPs. The industry’s current answer — the “AI PC”, a von Neumann machine with an NPU bolted on — is a transitional form, not the final one.

From the abstract
We argue for redesigning the machine around the model, from the hardware up. We name the result the Noeton (from Greek noesis, “the act of understanding”), and its organizing principle the Model-Native Architecture. We ground each principle in existing research — the memory wall, processing-in-memory, CXL pooling, wafer-scale integration, deterministic dataflow processors, and emerging LLM operating systems — and synthesize them into a coherent reference design. We do not build the Noeton; this is a position paper, offered as a target worth arguing about, with its costs taken seriously.
Roofline analysis: LLM decode is bandwidth-bound
Decode sits on the bandwidth ceiling — a faster NPU lifts a ceiling it never touches
Core claims

Five principles define the Model-Native Architecture

Each principle is backed by existing systems research: HBM-PIM, UPMEM, CXL pooling, TPU/Groq/SambaNova dataflow, MemGPT/AIOS…

P1

Memory-centric organization

Weights and the KV cache are first-class citizens, served in place by processing-in-memory and disaggregated, pooled memory — not streamed through a core.

P2

Model-native compute

A tensor / attention dataflow fabric does the heavy lifting; the classical CPU is demoted to a housekeeping coordinator.

P3

The model is the OS

An LLM as the kernel: agents are processes, tools are syscalls, vector stores are the filesystem.

P4

Network-mandatory, tiered cognition

A small on-device model provides only a degraded-mode floor; full capability comes from networked weight pools across device, edge, and cloud.

P5

Intent-driven interaction

The user’s unit of work is an intent expressed against context, not a command issued against data.

Architecture

From contrast diagram to five-layer stack

All diagrams are the paper’s original vector figures (TikZ → SVG).

Fig 1 · von Neumann machine vs Noeton: from compute-centered to memory-resident-model-centered
Fig 1 · von Neumann machine vs Noeton: from compute-centered to memory-resident-model-centered
Fig 2 · The Noeton five-layer stack: L1 memory-centric substrate → L5 intent interface
Fig 2 · The Noeton five-layer stack: L1 memory-centric substrate → L5 intent interface
Fig 3 · Roofline argument: LLM decode is bandwidth-bound; a faster NPU lifts an unused ceiling
Fig 3 · Roofline argument: LLM decode is bandwidth-bound; a faster NPU lifts an unused ceiling
Fig 4 · Tiered cognition across device, edge, and cloud
Fig 4 · Tiered cognition across device, edge, and cloud
Papers

Open access, in two languages

PDF

Beyond the Computer: The Noeton — A Model-Native Architecture for the AI Era

English edition v2 · new §12 "Industry Trajectory (2024–2026)" · companion: evidence wall
Download English PDF
PDF

超越计算机:Noeton —— 一种面向 AI 时代的模型原生架构

Chinese edition · ~22 pages · single-column preprint · XeLaTeX
下载中文版
computer architecturelarge language modelsmemory wallprocessing-in-memorymemory disaggregationdomain-specific architectureLLM operating systemsdevice-cloud inference